1. Technical Field
The present invention relates to a semiconductor package and a method of fabricating the same. More specifically, the present invention is directed to a wafer level package and a method of fabricating the same.
2. Background of the Related Art
Generally, semiconductor manufacturing can be divided into two kinds of processes. The two kinds of processes are a front-end process to manufacture IC chips on a wafer by means of processes such as photolithography/deposition/etch, and a back-end process involving assembling and packaging each of the IC chips. Four significant functions of the packaging process are as follows:                1. Protection of the IC chips from the environment and handling damage.        2. Completing interconnections to carry electrical signals into and out of the IC chip.        3. Providing physical support for the IC chip.        4. Heat dissipation.        
In addition to the above explained functions, as semiconductor devices continue to be scaled down and as portable electronic devices are becoming popular, several additional functions, such as the enhancement of electrical performance and reductions in cost, weight and thickness, are being required from the packaging process. Recently in order to satisfy this technological demand, methods of using an interconnection structure which penetrates semiconductor chips to electrically connect the semiconductor chips have been proposed.
FIG. 1 is a cross-sectional view of a conventional stack-type package.
Referring to FIG. 1, a plurality of package units 60 are stacked sequentially on an interconnection substrate 20 having a connection terminal 22 and a bump 24 coupled to the connection terminal 22. Each of the package units 60 includes a semiconductor chip 10 having input/output pads 12 and an interconnection structure penetrating the semiconductor chip 10 to be connected to the input/output pads 12.
More specifically, the interconnection structure includes a bottom conductive pattern 30 which is connected to the input/output pad 12 and covers an inside wall of a via hole 11 penetrating the semiconductor chip 10, a plug pattern 40 filling the via hole 11 having the bottom conductive pattern 30, and an under-bump metallization (UBM) pattern 50 disposed on the plug pattern 40. Here, the plug pattern 40 may be divided into a plug part 44 filling the via hole 11, a connecting part 46 which is disposed on the plug part 44 to be extended to a top surface of the input/output pad 12, and a protruding part 42 which is disposed under the plug part 44 to protrude from a bottom surface of the semiconductor chip 10. The protruding part 42 and the plug part 44 may be formed by the same process or by separate fabricating processes.
According to the above explained conventional art, the package units 60 and the interconnection substrate 20 are electrically connected through the interconnection structure. More specifically, the protruding part 42 of one package unit is electrically connected to the UBM pattern 50 of another package unit or the connection terminal 22 of the interconnection substrate 20. Since the conventional wire bonding process can be minimized or eliminated by the afore-mentioned connecting method, this package technology using the plug structure is especially desirable in application fields in which a high performance and a small form-factor are required.
However, according to conventional art, in order to construct the via hole 11 and an interconnection structure penetrating the via hole 11, a complicated fabricating process is required which may increase the fabricating costs and increase the number of defective products. In addition, in order to secure stability of the electrical connections, a solder bump may be formed at a bottom surface of the package units 60. (For example, the protruding part 42 may be substituted with a solder bump). However, contrary to the technical trend toward a small thickness in the packaging art, this method results in an increase of the space h1 between the package units 60 and an increase of the space h2 between the package unit 60 and the interconnection substrate 20. Also, in the conventional packaging scheme, a break of the protruding part 42 may often occur because a mechanical force may be focused on the protruding part 42 during the process for adhering semiconductor chips.
The present invention addresses these and other disadvantages of the conventional art.